1. Technical Field
This invention is related to the field of integrated circuit implementation, and more particularly to the implementation of clock management circuits.
2. Description of the Related Art
Computing systems may include one or more systems-on-a-chip (SoC), which may integrate a number of different functions, such as, graphics processing, onto a single integrated circuit. With numerous functions included in a single integrated circuit, chip count may be kept low in mobile computing systems, such as tablets, for example, which may result in reduced assembly costs, and a smaller form factor for such mobile computing systems.
Some SoC designs may support a variety of operational frequencies for a variety of reasons. For example, a specific frequency may be required for a certain communications protocol, such as, for example, Universal Serial Bus (USB) or Ethernet. In other embodiments, a system frequency may be increased or decreased to either increase performance of the system or reduce power consumption of the system depending on the needs of the system at any given time. In order to support adjustable frequencies, clock circuits may include a closed loop clock generating circuit such as, for example, a Phase-Locked Loop (PLL) or Frequency-Locked Loop (FLL). PLLs and FLLs may allow for a wide range of clock frequencies to be generated.
In some SoC designs, a voltage regulator may be used to maintain the voltage level of the power supply used throughout the SoC to prevent the voltage level from rising to a level which may damage the circuits. The method on which many voltage regulator designs operate may be susceptible to problems when there is a sudden change in the current consumption from the logic circuits to which the regulator is providing power. A sudden increase in current consumption may cause a temporary drop in the voltage level of the output of the regulator while the regulator adjusts to compensate. For example, if the SoC is consuming an average of 10 mA and the SoC suddenly increases power consumption to an average of 100 mA due to a performance shift such as an increase in the system frequency, then the output voltage of the voltage regulator may drop from the normal regulated voltage level until the regulator adjusts to compensate for the new current demand from the SoC and settles back to the normal regulated voltage level. This drop in the voltage level may be referred to as voltage droop. If the voltage droop results in a voltage level that is below a minimum voltage level necessary to operate the logic circuits, even briefly, a logic state within the logic circuits may be corrupted, which may lead to indeterminate behavior and a possible processing exception.
A method is desired in which a system frequency of an SoC may be modified from any supported frequency to any other supported frequency without risk of voltage droop of a voltage regulator falling below a minimum safe operating voltage level. Systems and methods for achieving a safe change in system frequency are presented below.